The present invention relates to a playback clock extracting apparatus suitable for extracting from a differential wave-form signal played back from a recording medium, a playback clock synchronous in phase with the signal.
In case digital data recorded on a magnetic tape or the like is played back from the magnetic tape, a playback clock is extracted from a playback differential wave-form signal and the digital data is detected synchronously with the extracted playback clock. The played back signals contain in their transitional portions synchronous information, i.e., information on phase of the playback clock.
FIG. 1 shows a configuration of a conventional playback clock extracting apparatus. In FIG. 1, an analog equalizer 10 receives a playback differential wave-form signal and outputs it through wave-form equalization. An analog-to-digital converter 11 samples, at a playback clock (sampling clock) of recording rate, a signal outputted by the analog equalizer 10 and outputs the signal as digital data. A flip-flop 101 for making timing adjustment receives and latches this signal and outputs the signal as playback data. A ternary decision circuit 12 makes a ternary decision of the inputted playback data and outputs a result of the decision. Namely, if the inputted playback data is larger than a positive threshold level in FIGS. 2A-C a decision of "1" is made. Meanwhile, if the inputted playback data is smaller than a negative threshold level in FIG. 2, a decision of "-1" is made. In cases other than the above two cases, a decision of "0" is made.
A voltage controlled oscillator 14 adjusts frequency on the basis of an inputted phase error output and outputs a generated playback clock. Namely, if the inputted phase error output is a positive value and a negative value, the frequency of the generated playback clock becomes momentarily large and small, respectively. This playback clock is delivered to the analog-to-digital converter 11 and flip-flops 101, 131 and 132.
An arithmetic circuit 13 for calculating a phase error is constituted by the two flip-flops 131 and 132 for making timing adjustment, a subtracter 133 and a multiplier 134. The current playback data is subjected to a delay of two clock cycles of the playback clock by the flip-flops 131 and 132. Then, playback data preceding the current playback data by two clock cycles of the playback clock is subtracted from the current playback data in the subtracter 133. Subsequently, this result of subtraction is multiplied by the result of the decision outputted from the ternary decision circuit 12 in the multiplier 134 and this result of multiplication is outputted as the phase error output representing error of sampling phase.
Meanwhile, since a delay of one clock cycle of the playback clock is made from output of the analog-to-digital converter 11 to an output of the ternary decision circuit 12 by the flip-flop 101 and a delay of two clock cycles of the playback clock is made from the output of the analog-to-digital converter 11 to an output of the flip-flop 132 by the two flip-flops 131 and 132, a result of a decision on data which precedes, by one clock cycle of the playback clock, data inputted to a (-) terminal of the subtracter 133 and follows, by one clock cycle of the playback clock, data inputted to a (+) terminal of the subtracter 133 is delivered from the ternary decision circuit 12 to the multiplier 134. A loop including the analog-to-digital converter 11, the arithmetic circuit 13 and the voltage controlled oscillator 14 constitute a phase locked loop (PLL) circuit.
FIGS. 2A-C are timing charts showing relationship between the playback differential wave-form signal and the playback clock (sampling clock) in the conventional playback clock extracting apparatus of FIG. 1. In FIGS. 2A-C, digital data obtained through sampling at sampling points a to h of the playback clock (sampling clock) in the analog-to-digital converter 11 has values A to H, respectively. In the conventional playback clock extracting apparatus of FIG. 1, since the playback differential wave-form signal is subjected to sampling at each rise of the playback clock by the analog-to-digital converter 11 and then, is latched by the flip-flop 101, the playback data assumes the values A to H.
FIG. 2A illustrates a case in which the playback clock is in phase with the playback differential wave-form signal. In this case, a result of a decision made by the ternary decision circuit 12 is other than "0" when the result of the decision is "1" for the value C and is "-1" for the value F. At this time, the phase error output from the arithmetic unit 13 assumes a value of (B-D) {=(B-D).times.(1)} and a value of (G-E) {=(E-G).times.(-1)}, respectively. In phase of FIG. 2A, since both of the values of (B-D) and (G-E) are substantially zero, the frequency of the playback clock generated by the voltage controlled oscillator 14 is held and the playback clock generated by the voltage controlled oscillator 14 is held in phase with the playback differential wave-form signal.
FIG. 2B illustrates a case in which the playback clock leads in phase the playback differential wave-form signal. Also in this case, a result of a decision made by the ternary decision circuit 12 is other than "0" when the result of the decision is "1" for the value C and is "-1" for the value F. At this time, the phase error output from the arithmetic unit 13 assumes a value of (B-D) {=(B-D).times.(1)} and a value of (G-E) {=(E-G).times.(-1)}, respectively. In phase of FIG. 2B, since both of the values of (B-D) and (G-E) are negative, the frequency of the playback clock generated by the voltage controlled oscillator 14 becomes small momentarily and the playback clock generated by the voltage controlled oscillator 14 shifts in such a direction as to lag in phase relative to the playback differential wave-form signal, i.e., in such a direction as to be in phase with the playback differential wave-form signal.
FIG. 2C illustrates a case in which the playback clock lags in phase behind the playback differential wave-form signal. Also in this case, a result of a decision made by the ternary decision circuit 12 is other than "0" when the result of the decision is "1" for the value C and is "-1" for the value F. At this time, the phase error output from the arithmetic unit 13 assumes a value of (B-D) {=(B-D).times.(1)} and a value of (G-E) {=(E-G).times.(-1)}, respectively. In phase of FIG. 2C, since both of the values of (B-D) and (G-E) are positive, the frequency of the playback clock generated by the voltage controlled oscillator 14 becomes large momentarily and the playback clock generated by the voltage controlled oscillator 14 shifts in such a direction as to lead in phase the playback differential wave-form signal, i.e., in such a direction as to be in phase with the playback differential wave-form signal.
Therefore, in the conventional playback clock extracting apparatus of FIG. 1, automatic control is performed so as to bring the playback clock into phase with the playback differential wave-form signal such that signals are played back as accurately as possible.
However, the following problems (1) to (4) arise in the conventional playback clock extracting apparatus of FIG. 1.
(1) At continuously changing portions of the playback differential wave-form signal, it is impossible to fetch phase information.
(2) According to characteristics of a magnetic tape or the like, a phenomenon (hereinafter, referred to as "phase jitter") may happen that the phase of the generated playback clock is shifted additionally from the phase of the playback differential wave-form signal in a state where the playback differential wave-form signal is not subjected to wave-form equalization or is subjected to incomplete wave-form equalization. As a result, signals cannot be played back accurately. When wave-form equalization is performed digitally after analog-to-digital conversion in order to solve this problem, wave-form equalization enters the loop of the PLL circuit, so that convergence of the wave-form equalization and the PLL should be performed simultaneously and thus, the convergence is delayed or is performed erroneously due to lack of information content. Hence, it is essential that analog wave-form equalization be performed prior to analog-to-digital conversion.
(3) In order to give a decision margin to the ternary decision circuit 12, the positive and negative threshold levels are required to be set small and large, respectively. As a result, a state (hereinafter, referred to as a "phase convergent point") in which the playback clock is finally converged into phase with the playback differential wave-form signal erroneously exists, in addition to a proper phase convergent point, also in case the phase of the playback clock is shifted through a half of a period and thus, signals may not be played back accurately.
(4) At portions of the playback differential wave-form signal, in which the playback differential wave-form signal is changing continuously, a large offset is generated in the momentary phase error output. Here, the term "offset" means a residual signal component in the momentary phase error output. The offset is finally cancelled by the integral effect of the PLL circuit, but affects the momentary phase of the generated playback clock, thus resulting in production of momentary phase jitter in the playback clock.
The above mentioned problem (1) is described below in more detail. Suppose that results of ternary decision on signal string {an} are as follows, the following phase error outputs are obtained.
______________________________________ (Signal string) (Ternary decision) (Phase error output) ______________________________________ a1 0 a2 0 0 a3 1 0 a4 0 a2-a4 a5 0 0 a6 -1 0 a7 1 a7-a5 a8 -1 a6-a8 a9 1 a9-a7 a10 0 a8-a10 ______________________________________
When values other than "0" continue in the results of ternary decision, the signals a7 and a8 are cancelled completely and the signals a6 and a9 do not contain phase information.
Then, regarding the problem (2) referred to above, a reason why phase jitter is produced in the generated playback clock is described below in more detail. Ideally, the playback differential wave-form signal from a magnetic tape or the like has satisfactory differential characteristics. Thus, when the playback clock is in phase with the playback differential wave-form signal in the analog-to-digital converter 11 of FIG. 1, the sampling values B and D at the points b and d are substantially zero as shown in FIG. 2A. However, actually, frequency characteristics of the playback differential wave-form signal deteriorate due to characteristics of the recording medium itself and a magnetic playback system. Therefore, in order to obtain ideal differential characteristics, wave-form equalization should be performed. In case the playback differential wave-form signal is not subjected to wave-form equalization or is subjected to incomplete wave-form equalization, the playback differential wave-form signal has differential characteristics which are greatly distorted greatly in the vicinity of zero-crossings.
FIG. 3 is a timing chart showing the relationship between the playback differential wave-form signal subjected to incomplete wave-form equalization and the playback clock in the conventional playback clock extracting apparatus of FIG. 1. In FIG. 3, digital data obtained through sampling at sampling points a to h of the playback clock (sampling clock) in the analog-to-digital converter 11 has values A to H, respectively. In FIG. 3, although the playback clock is in phase with the playback differential wave-form signal, the playback differential wave-form signal subjected to incomplete wave-form equalization is distorted in the vicinity of zero-crossings, i.e., points d and g. Hence, both of values of (B-D) and (G-E) of the phase error output from the arithmetic unit 13 are positive, so that the frequency of the playback clock generated by the voltage controlled oscillator 14 becomes large momentarily and thus, the playback clock leads in phase the playback differential wave-form signal.
Namely, if phase error is calculated in a state where the playback differential wave-form signal is not subjected to wave-form equalization or is subjected to incomplete wave-form equalization, phase jitter is produced in the generated playback clock.
Subsequently, concerning the above mentioned problem (3), a reason why the wrong phase convergent point exists is described below in more detail. FIGS. 4A and B are timing charts showing the relationship between the playback differential wave-form signal and the playback clock (sampling clock) in the conventional playback clock extracting apparatus of FIG. 1. In FIGS. 4A and B, digital data obtained through sampling at sampling points a to h of the playback clock (sampling clock) has values A to H, respectively.
FIG. 4A illustrates a case in which the playback clock leads in phase by about 170.degree. the playback differential wave-form signal. In this case, a result of a decision made by the ternary decision circuit 12 is other than "0" when the result of the decision is "1" for the values C and D and is "-1" for the values F and G. At this time, the phase error output from the arithmetic unit 13 assume values of (B-D), (C-E), (G-E) and (H-F).
In FIG. 4A, the negative value of (B-D) and the positive value of (C-E) are sequentially given, as the phase error output, from the arithmetic circuit 13 to the voltage controlled oscillator 14. Furthermore, the negative value of (G-E) and the positive value of (H-F) are sequentially delivered from the arithmetic unit 13 to the voltage controlled oscillator 14. The values of (B-D) and (C-E) cancel substantially cancel each other, but do not eliminate each other completely so as to total slightly positive, i.e., {(C-E)+(B-D)}&gt;0. Similarly, the values of (G-E) and (H-F) substantially cancel each other, but do not eliminate each other completely so as to total slightly positively, i.e., {(H-F)+(G-E)}&gt;0. Accordingly, the frequency of the playback clock generated by the voltage controlled oscillator 14 becomes large momentarily and the playback clock is shifted so as to lead in phase the playback differential wave-form signal. When the phase has finally led through not 0.degree. but just a half of a period, i.e., 180.degree., phase is converged. At this time, wrong playback signals are outputted.
FIG. 4B illustrates a case in which the playback clock leads in phase by about 190.degree. the playback differential wave-form signal, namely, lags in phase by about 170.degree. behind the playback differential wave-form signal. Also in this case, a result of a decision made by the ternary decision circuit 12 is other than "0" when the result of the decision is "1" for the values C and D and is "-1" for the values F and G. At this time, the phase error output from the arithmetic unit 13 assumes values of (B-D), (C-E) , (G-E) and (H-F).
In FIG. 4B, the negative value of (B-D) and the positive value of (C-E) are sequentially given, as the phase error output, from the arithmetic circuit 13 to the voltage controlled oscillator 14. Furthermore, the negative value of (G-E) and the positive value of (H-F) are sequentially delivered from the arithmetic unit 13 to the voltage controlled oscillator 14. The values of (B-D) and (C-E) cancel substantially cancel each other, but do not eliminate each other completely so as to total slightly negative, i.e., {(C-E)+(B-D)}&lt;0. Similarly, the values of (G-E) and (H-F) substantially cancel each other, but do not eliminate each other completely so as to total slightly negative, i.e., {(H-F)+(G-E)}&lt;0. Accordingly, the frequency of the playback clock generated by the voltage controlled oscillator 14 becomes small momentarily and the playback clock is shifted so as to lag in phase behind the playback differential wave-form signal. When the phase has finally lagged through not 0.degree. but just a half of a period, i.e., 180.degree., phase is converged. At this time, wrong playback signals are outputted.
FIG. 5 shows relationship between phase lead of the playback clock and phase error output in the conventional playback clock extracting apparatus of FIG. 1. A point where the phase of the playback clock has an angle of 0.degree. relative to that of the playback differential wave-form signal is a proper phase convergent point. However, when phase of the playback clock has deviated through about a half of a period (.+-.180.degree.) from that of the playback differential wave-form signal as shown in FIG. 4, such a phenomenon happens that the results of the decision are continuously "1" or "-1" for two clock cycles. In the differential wave-form, this phenomenon does not happen as long as sampling is performed at the proper phase.
In other words, in addition to the proper phase convergent point where phase of the playback clock has an angle of 0.degree. (or .+-.360.degree.) relative to that of the playback differential wave-form signal, the wrong phase convergent point also exists at a point where the phase of the playback clock deviates through a half of a period (.+-.180.degree.) from that of the playback differential wave-form signal. As a result, it becomes impossible to playback signals at high fidelity.
Then, regarding the above problem (4), a reason why momentary phase jitter is produced in the generated playback clock is described below in more detail. Suppose that results of ternary decision on signal string {an} are as follows, the following phase error outputs are obtained.
______________________________________ (Signal string) (Ternary decision) (Phase error output) ______________________________________ a1 0 a2 0 0 a3 1 0 a4 0 a2-a4 a5 0 0 a6 -1 0 a7 1 a7-a5 a8 -1 a6-a8 a9 1 a9-a7 a10 0 a8-a10 ______________________________________
Here, when the results of ternary decision are other than "0" continuously, values of (a7-a5) and (a8-a10) become extremely large even if the relay clock is in phase with the playback differential wave-form signal. As a result, since a momentary large offset is produced in the phase error output, momentary phase jitter is produced in the playback clock.